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S71PL512ND0 MirrorBitTM Flash Family
Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
Notice to Readers: This document indicates states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that a product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication Number S71PL512ND0_00
Revision A
Amendment 2
Issue Date December 6, 2005
Preliminary
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets will contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with DC Characteristics table and AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
ii
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005
S71PL512ND0 MirrorBitTM Flash Family
Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
This document contains information for the S71PL512ND0 MirrorBit MCP product. Refer to the S29PL-N_M0, Rev A2 (S29PL256N/129N/127N) data sheet (included in this document) for full electrical specifications for the Flash memory component. Refer to the PSRAM_15, Rev A2 (PSRAM Type 2), data sheet (included in this document) for full electrical specifications for the pSRAM component. The S71PL512ND0 Series is a Multi-Chip Product (MCP) and consists of: Two S29PL256N Flash memory die One 128M pSRAM die of Type 2
Distinctive Characteristics
MCP Features
Speed -- Flash: 70 ns -- pSRAM: 70 ns Packages -- 84-Ball Fine-Pitch Ball Grid Array (FBGA), 8.0 x 11.6 x 1.4 mm Operating Temperature Range -- Temperature Range of -25C to +85C
Product Selector Guide
MCP S71PL512ND0-5B Flash 2 x S29PL256N pSRAM Density 128M pSRAM Type Type 2
Publication Number S71PL512ND0_00
Revision A
Amendment 2
Issue Date December 6, 2005
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice. This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product
Preliminary
Contents
Notice On Data Sheet Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Input/Output Descriptions and Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 Connection Diagrams/Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Special Handling Instructions for FBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 FEB084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.1 Connection Diagram - FEB084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 Physical Dimensions - FEB084, 8.0 x 11.6 mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5 Input/Output Descriptions and Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1 Device Operation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.1.1 Dual Chip Enable Device Description and Operation (PL129N Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.2 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9.2.1 Non-Page Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9.2.2 Page Mode Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9.3 Autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 9.4 Program/Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4.1 Single Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.4.2 Write Buffer Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.4.3 Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.4.4 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.5 Erase Suspend/Erase Resume Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.4.6 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.4.7 Accelerated Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4.8 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.4.9 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 9.5 Simultaneous Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9.7 Hardware Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.8 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 Persistent Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 Dynamic Protection Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.4 Persistent Protection Bit Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.5 Password Protection Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6 Advanced Sector Protection Software Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.7 Hardware Data Protection Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.7.1 WP# Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.7.2 Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.7.3 Write Pulse Glitch Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.7.4 Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 Power Conservation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.1 Standby Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2 Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.3 Hardware RESET# Input Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.4 Output Disable (OE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12 Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2 S71PL512ND0 MirrorBitTM Flash Family S71PL512ND0_00_A2 December 6, 2005
Preliminary
12.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.3 Secured Silicon Sector Entry and Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.2 Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.6 VCC Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.7.1 DC Characteristics (VCC = 2.7 V to 3.6 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.7.2 DC Characteristics (VCC = 2.7 V to 3.1 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.8.1 Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.8.2 Read Operation Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.8.3 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 13.8.4 Erase/Program Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.8.5 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.8.6 BGA Ball Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14 Commonly Used Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 15 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 15.1 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 16 Revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Product Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 18 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 19 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 19.1 Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 20 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 21 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 22 DC Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 23 Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 24 DC and Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 24.1 Common . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 24.2 16M pSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 24.3 32M pSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 24.4 64M pSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 24.5 128M pSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 25 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 25.1 Test Conditions (Test Load and Test Input/Output Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 26 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.1 Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 27.2 Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 28 pSRAM Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 28.1 Revision A0 (February 16, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 28.2 Revision A1 (June 11, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 28.3 Revision A2 (February 3, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 29 MCP Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
December 6, 2005 S71PL512ND0_00_A2
S71PL512ND0 MirrorBitTM Flash Family
3
Preliminary
Tables
Table 2.1 Table 5.1 Table 8.1 Table 8.2 Table 8.3 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 9.6 Table 9.7 Table 9.8 Table 9.9 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PL256N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PL127N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PL129N Sector and Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Dual Chip Enable Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Word Selection within a Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Autoselect Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Autoselect Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Autoselect Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single Word Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Write Buffer Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Sector Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 9.10 Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 9.11 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9.12 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9.13 Program Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9.14 Program Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 9.15 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 9.16 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9.17 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9.18 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 9.19 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 10.1 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 10.2 Sector Protection Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 12.1 Secured Silicon Sector Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 12.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 12.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 12.4 Secured Silicon Sector Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 13.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 15.1 Memory Array Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 15.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 15.3 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 15.4 System Interface String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 15.5 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 15.6 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005
Preliminary
Figures
Figure 4.1. Figure 4.2. Figure 5.1 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Figure 10.1 Figure 10.2 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Figure 13.7 Figure 13.8 Figure 13.9 Connection Diagram - 84-ball Fine-Pitch Ball Grid Array .......................................................................... 9 Physical Dimensions - 84-ball Fine-Pitch Ball Grid Array .........................................................................10 Logic Symbols - PL256N, PL129N, and PL127N .....................................................................................12 Single Word Program Operation ..........................................................................................................23 Write Buffer Programming Operation ...................................................................................................26 Sector Erase Operation ......................................................................................................................28 Write Operation Status Flowchart ........................................................................................................35 Simultaneous Operation Block Diagram for S29PL256N and S29PL127N ...................................................39 Simultaneous Operation Block Diagram for S29PL129N ..........................................................................40 Advanced Sector Protection/Unprotection .............................................................................................44 Lock Register Program Algorithm.........................................................................................................48 Maximum Negative Overshoot Waveform .............................................................................................55 Maximum Positive Overshoot Waveform ...............................................................................................55 Test Setup .......................................................................................................................................56 Input Waveforms and Measurement Levels...........................................................................................57 VCC Power-Up Diagram ......................................................................................................................57 Read Operation Timings .....................................................................................................................60 Page Read Operation Timings .............................................................................................................61 Reset Timings...................................................................................................................................61 Program Operation Timings ................................................................................................................63
Figure 13.10 Accelerated Program Timing Diagram ..................................................................................................63 Figure 13.11 Chip/Sector Erase Operation Timings ...................................................................................................64 Figure 13.12 Back-to-back Read/Write Cycle Timings ...............................................................................................64 Figure 13.13 Data# Polling Timings (During Embedded Algorithms)............................................................................65 Figure 13.14 Toggle Bit Timings (During Embedded Algorithms).................................................................................65 Figure 13.15 DQ2 vs. DQ6 ....................................................................................................................................66 Figure 19.1 Figure 19.2. Figure 25.1 Figure 27.1 Figure 27.2. Figure 27.3. Figure 27.4. Figure 27.5. Figure 27.6. Figure 27.7. Power Up 1 (CS1# Controlled) ............................................................................................................79 Power Up 2 (CS2 Controlled) ..............................................................................................................79 Output Load .....................................................................................................................................82 Timing Waveform of Read Cycle(1)......................................................................................................83 Timing Waveform of Read Cycle(2)......................................................................................................84 Timing Waveform of Page Cycle (Page Mode Only).................................................................................84 Write Cycle #1 (WE# Controlled) ........................................................................................................85 Write Cycle #2 (CS1# Controlled) .......................................................................................................85 Timing Waveform of Write Cycle(3) (CS2 Controlled) .............................................................................86 Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) .....................................................................86
December 6, 2005 S71PL512ND0_00_A2
S71PL512ND0 MirrorBitTM Flash Family
5
Preliminary
1
Ordering Information
The ordering part number is formed by a valid combination of the following: S71PL 512 N D0 JA W 5B 0
Packing 0 = 2 = 3 = Type Tray 7-inch Tape and Reel 13-inch Tape and Reel
Model Number 5B = 8.0x11.6 mm, 84 ball TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE AND MATERIAL JA = Very Thin Fine-Pitch MCP-compatible, 1.4 mm BGA, Lead (Pb)-free Compliant Package JF = Very Thin Fine-Pitch MCP-compatible 1.4 mm BGA, Lead (Pb)-free Package Chip Contents D0 = 128 Mb pSRAM PROCESS TECHNOLOGY N = 110 nm MirrorBitTM Technology FLASH DENSITY 512 = 512 Mb DEVICE FAMILY S71PL = 3.0 Volt-only Simultaneous Read/Write, Page Mode Same Die Stack Flash Memory
Valid Combinations Base Ordering Part Number S71PL512ND0 Package Type, Material, & Temperature Range JAW, JFW Model Number 5B Packing Type 0, 2, 3 (Note 1) Speed Option 70 pSRAM Type Type 2
Package Type (Note 2) FEB084 8.0x11.6 mm 84-ball MCP-Compatible (FBGA)
Notes:
1. 2. Type 0 is standard. Specify other options as required. BGA package marking omits leading S and packing type designator from ordering part number.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
6
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005
Preliminary
2
Input/Output Descriptions and Logic Symbol
Table 2.1 identifies the input and output package connections provided on the device.
Table 2.1
Symbol
A23- A0 DQ15 - DQ0 F1-CE# F2-CE# R-CE1# R-CE2 OE# WE# RY/BY# UB# LB# RESET# WP#/ACC F-VCCf R-VCC VSS NC I/O Input Input Input Input Input Input Output Input Input Input Input Supply Supply Supply Not connected
Input/Output Descriptions
Description
Type
Input Address Inputs (common) 16-bit data inputs/outputs (common) Chip Enable (Flash 1) Chip Enable (Flash 2) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable input Write Enable Ready/Busy Output (Flash 1) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM)
Hardware reset pin, Active Low (Flash 1) Hardware Write Protect/Acceleration pin (Flash) Flash 3.0 volt-only single power supply (see Product Selctor Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device ground (common) Pin Not Connected Internally
24 A23-A0
16 F1-CE# F2-CE# R-CE1# R-CE2 OE# WE# WP #/ACC RES ET# UB# LB# R Y/BY# DQ15-DQ0
December 6, 2005 S71PL512ND0_00_A2
S71PL512ND0 MirrorBitTM Flash Family
7
Preliminary
3
Block Diagram
VCCf
VCC F1-CE# WP#/ACC RESET# Flash-only Address Shared Address OE# WE# VSS RY/BY# F2-CE# Flash 2 Flash 1
VCCS
DQ15 to DQ0
VCC pSRAM/SRAM
IO15-IO0 CE#s UB#s LB#s CE2 CE# UB# LB#
Notes:
1. 2. RY/BY# is an open drain output. AMAX = A23.
8
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005
Preliminary
4
4.1
Connection Diagrams/Physical Dimensions
This section contains the I/O designations and package specifications for the S29PL256N.
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
4.2
FEB084, 8.0 x 11.6 mm
4.2.1 Connection Diagram - FEB084, 8.0 x 11.6 mm
A1 NC/DNU B2 RFU C2 RFU B3 RFU C3 A7 B4 RFU C4 R-LB# B5 F2-CE# C5 WP#/ACC B6 RFU C6 WE# B7 RFU C7 A8 B8 RFU C8 A11 B9 RFU C9 RFU
A10 NC/DNU
Legend
All Shared
pSRAM Only D2 A3 D3 A6 D4 R-UB# D5 F-RST# D6 R-CE2 D7 A19 D8 A12 D9 A15 Flash 1
E2 A2
E3 A5
E4 A18
E5 RY/BY# F5 RFU
E6 A20
E7 A9
E8 A13
E9 A21
F2 A1
F3 A4
F4 A17
F6 A23
F7 A10
F8 A14
F9 A22 Flash Shared
G2 A0
G3 VSS H3 OE#
G4 DQ1
G5 RFU
G6 RFU
G7 DQ6
G8 RFU
G9 A16 Flash 2 H9 RFU Reserved for Future Use/ Do Not Use
H2 F1-CE#
H4 DQ9
H5 DQ3
H6 DQ4
H7 DQ13
H8 DQ15
J2 R-CE1# K2 RFU L2 RFU M1
J3 DQ0
J4 DQ10
J5 F-VCC K5 DQ11
J6 R-VCC K6 RFU L6 RFU
J7 DQ12
J8 DQ7
J9 VSS K9 RFU L9 RFU M10
K3 DQ8 L3 RFU
K4 DQ2 L4 RFU
K7 DQ5 L7 RFU
K8 DQ14 L8 RFU
L5 F-VCC
Note: Top view--balls facing down.
Figure 4.1. December 6, 2005 S71PL512ND0_00_A2
Connection Diagram - 84-ball Fine-Pitch Ball Grid Array S71PL512ND0 MirrorBitTM Flash Family 9
Preliminary
4.2.2
Physical Dimensions - FEB084, 8.0 x 11.6 mm
D
A
D1 eD
10 9 8 7 6 5 4
0.15 C (2X)
SE 7 E1
E eE
INDEX MARK PIN A1 CORNER 9
3 2 1 MLKJ HG F EDC BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
M CAB MC
84X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD / SE 0.35 FEB 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.10 1.06 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.40 --1.26 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 8. 9 6 7 4. 5. NOTE 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3527 \ 16-038.21 \ 10.26.05
A2,A3,A4,A5,A6,A7,A8,A9, DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10, F1,F10,G1,G10,H1,H10,J1,J10, K1,K10, L1,L10, M2,M3,M4,M5,M6,M7,M8,M9
Figure 4.2.
Physical Dimensions - 84-ball Fine-Pitch Ball Grid Array
10
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005
S29PL-N MirrorBitTM Flash Family
S29PL256N, S29PL127N, S29PL129N, 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
Data Sheet
PRELIMINARY
General Description
The Spansion S29PL-N is the latest generation 3.0-Volt page mode read family fabricated using the 110 nm MirrorbitTM Flash process technology. These 8-word page-mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks. These devices offer fast page access times of 25 to 30 ns, with corresponding random access times of 65 ns, 70 ns, and 80 ns respectively, allowing high speed microprocessors to operate without wait states. The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and CE2#) that allow each half of the memory space to be controlled separately.
Distinctive Characteristics
Architectural Advantages
32-Word Write Buffer Dual Chip Enable Inputs (only for S29PL129N) -- Two CE# inputs control selection of each half of the memory space Single Power Supply Operation -- Full Voltage range of 2.7 - 3.6 V read, erase, and program operations for battery-powered applications -- Voltage range of 2.7 - 3.1 V valid for PL-N MCP products Simultaneous Read/Write Operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations 4-Bank Sector Architecture with Top and Bottom Boot Blocks 256-Word Secured Silicon Sector Region -- Up to 128 factory-locked words -- Up to 128 customer-lockable words Manufactured on 0.11 m Process Technology Data Retention of 20 years Typical Cycling Endurance of 100,000 Cycles per Sector Typical
Hardware Features
WP#/ACC (Write Protect/Acceleration) Input -- At VIL, hardware level protection for the first and last two 32 Kword sectors. -- At VIH, allows the use of DYB/PPB sector protection -- At VHH, provides accelerated programming in a factory setting Dual Boot and No Boot Options Low VCC Write Inhibit
Security Features
Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method locks combinations of individual sectors to prevent program or erase operations within that sector using a user defined 64-bit password
Performance Characteristics
Read Access Times (@ 30 pF, Industrial Temp.) Random Access Time, ns (tACC) Page Access Time, ns (tPACC) Max CE# Access Time, ns (tCE) Max OE# Access Time, ns (tOE) 65 25 65 25 70 30 70 30 80 30 80 30 Typical Program & Erase Times (typical values) (See Note) Typical Word Typical Effective Word (32 words in buffer) Accelerated Write Buffer Program Typical Sector Erase Time (32-Kword Sector) Typical Sector Erase Time (128-Kword Sector) 40 s 9.4 s 6 s 300 ms 1.6 s
Note: : Typical program and erase times assume the following
Current Consumption (typical values) 8-Word Page Read Simultaneous Read/Write Program/Erase Standby 6 mA 65 mA 25 mA 20 A S29PL-N 256 129 127 Package Options VBH084 8.0 x 11.6 mm, 84-ball
conditions: 25C, 3.0 V VCC, 10,000 cycles; checkerboard data pattern. VBH064 8.0 x 11.6 mm, 64-ball LAA064 11 x 13 mm, 64-ball Fortified BGA
Publication Number S29PL-N_M0 Revision A Amendment 4 Issue Date November 23, 2005
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Preliminary
5
Input/Output Descriptions and Logic Symbols
Table 5.1 identifies the input and output package connections provided on the device.
Table 5.1
Symbol
Amax - A0 DQ15 - DQ0 CE# OE# WE# VSS NC I/O Input Input Input Supply Not connected
Input/Output Descriptions
Description
Type
Input Address bus 16-bit data inputs/outputs/float Chip Enable input Output Enable input Write Enable Device ground Pin Not Connected Internally
RY/BY#
Output
Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Device Power Supply Hardware reset pin Chip Enable inputs for S29PL129 device
VCC RESET# CE1#, CE2#
Supply Input Input
max +1 Amax-A0 CE# OE# WE# WP#/ACC RESET# VCC RY/BY# DQ15 - DQ0 16
22
A21 - A0 CE1# CE2# OE# WE# WP#/ACC RESET# VCC RY/BY# DQ15 - DQ0
16
Notes:
1. Amax = 23 for the PL256N and 22 for the PL127N.
Logic Symbol - PL256N and PL127N
Logic Symbol - PL129N
Figure 5.1
Logic Symbols - PL256N, PL129N, and PL127N
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
6
Block Diagram
DQ15-DQ0 RY/BY# (See Note) VCC VSS Sector Switches Input/Output Buffers Erase Voltage Generator WE# State Control Command Register PGM Voltage Generator
RESET#
CE# OE#
Chip Enable Output Enable Logic
Data Latch
Amax - A3
Address Latch
VCC Detector
Timer
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A2-A0
Notes:
1. 2. 3. RY/BY# is an open drain output. Amax = A23 (PL256N), A22 (PL127N), A21 (PL129N). PL129N has two CE# pins CE1# and CE2#.
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Preliminary
7
Additional Resources
Visit www.amd.com and www.fujitsu.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices Simultaneous Read/Write vs. Erase Suspend/Resume MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Design-In Scalable Wireless Solutions with Spansion Products Common Flash Interface Version 1.4 Vendor Specific Extensions
Specification Bulletins
Contact your local sales office for details.
Drivers and Software Support
Spansion Low-Level Drivers Enhanced Flash Drivers Flash File System
CAD Modeling Support
VHDL and Verilog IBIS ORCAD
Technical Support
Contact your local sales office or contact Spansion LLC directly for additional technical support: Email US and Canada: HW.support@amd.com Asia Pacific: asia.support@amd.com Europe, Middle East, and Africa Japan: http://edevice.fujitsu.com/jp/support/tech/#b7 Frequently Asked Questions (FAQ) http://ask.amd.com/ http://edevice.fujitsu.com/jp/support/tech/#b7 Phone US: (408) 749-5703 Japan (03) 5322-3324
Spansion LLC Locations
915 DeGuigne Drive, P.O. Box 3453 Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com
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Preliminary
8
Product Overview
The S29PLxxxN family consists of 256 and 128 Mb, 3.0 volts-only, simultaneous read/write page-mode read Flash devices that are optimized for wireless designs of today that demand large storage array and rich functionality, while requiring low power consumption. These products also offer 32-word buffer for programming with program and erase suspend/resume functionality. Additional features include: Advanced Sector Protection methods for protecting an individual or group of sectors as required, 256-word of secured silicon area for storing customer and factory secured information Simultaneous Read/Write operation
8.1
Memory Map
The S29PL-N devices consist of 4 banks organized as shown in Tables 8.1, 8.2, and 8.3.
Table 8.1
Bank Bank Size Sector Count Sector Size (KB) 64 4 A 4 MB 64 64 64 256 15 ... 256 256 B 12 MB 48 ... 256 256 C 12 MB 48 ... 256 256 15 ... 256 D 4 MB 4 64 64 64 64
PL256N Sector and Memory Address Map
Sector/ Sector Range SA00 SA01 SA02 SA03 SA04 ... SA018 SA19 ... SA66 SA67 ... SA114 SA115 ... SA129 SA130 SA131 SA132 SA133 Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-03FFFFh 1E0000h-1FFFFFh 200000h-21FFFFh 7E0000h-7FFFFFh 800000h-81FFFFh DE0000h-DFFFFFh E00000h-E1FFFFh FC0000h-FDFFFFh FE0000h-FE7FFFh FE8000h-FEFFFFh FF0000h-FF7FFFh FF8000h-FFFFFFh Sector Starting Address Sector Ending Address ... ... ... ... Sector Starting Address Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) Sector Starting Address Sector Ending Address (see note) Sector Starting Address - Sector Ending Address Notes
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
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Preliminary
Table 8.2
Bank Bank Size Sector Count Sector Size (KB) 64 4 A 2 MB 64 64 64 256 7 ... 256 256 B 6 MB 24 ... 256 256 C 6 MB 24 ... 256 256 7 ... 256 D 2 MB 4 64 64 64 64
PL127N Sector and Memory Address Map
Sector/ Sector Range SA00 SA01 SA02 SA03 SA04 ... SA10 SA11 ... SA34 SA35 ... SA58 SA59 ... SA65 SA66 SA67 SA68 SA69 Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-03FFFFh 0E0000h-0FFFFFh 100000h-11FFFFh 3E0000h-3FFFFFh 400000h-41FFFFh 6E0000h-6FFFFFh 700000h-71FFFFh 7C0000h-7DFFFFh 7E0000h-7E7FFFh 7E80000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7FFFFFh Sector Starting Address Sector Ending Address ... ... ... ... Sector Starting Address - Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) Sector Starting Address Sector Ending Address (see note) Sector Starting Address Sector Ending Address Notes
Note: Ellipses indicate that other addresses in sector range follow the same pattern.
Table 8.3
Bank Bank Size Sector Count Sector Size (KB) 64 4 1A 2 MB 64 64 64 256 7 ... 256 256 1B 6 MB 24 ... 256 256 2A 6 MB 24 ... 256 256 7 ... 256 2B 2 MB 4 64 64 64 64 VIH VIL
PL129N Sector and Memory Address Map
CE2# Sector/ Sector Range SA00 SA01 SA02 SA03 VIH SA04 ... SA10 SA11 ... SA34 SA35 ... SA58 SA59 ... VIL SA65 SA66 SA67 SA68 SA69 Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-03FFFFh 0E0000h-0FFFFFh 100000h-11FFFFh 3E0000h-3FFFFFh 000000h-01FFFFh 2E0000h - 2FFFFFh 300000h-31FFFFh 3C0000h-3DFFFFh 3E0000h-3E7FFFH 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh Sector Starting Address Sector Ending Address ... ... ... ... Sector Starting Address - Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) First Sector, Sector Starting Address Last Sector, Sector Ending Address (see note) Sector Starting Address Sector Ending Address (see note) Sector Starting Address Sector Ending Address Notes
CE1#
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Preliminary
9
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, and reset features of the Flash devices. Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command registers (see Table 15.1 and Table 15.2). The command register itself does not occupy any addressable memory location. Instead, the command register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the function of the device. Writing incorrect address and data values or writing them in an improper sequence can place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
9.1
Device Operation Table
The device must be setup appropriately for each operation. Table 9.1 describes the required state of each control pin for any particular operation.
Table 9.1
Operation Read Write Standby Output Disable Reset CE# L L H L X OE# L H X H X WE# H L X H X
Device Operation
WP#/ACC X X (See Note) X X X Addresses (Amax - A0) AIN AIN AIN AIN AIN DQ15 - DQ0 DOUT DIN High-Z High-Z High-Z
RESET# H H H H L
Legend: L = Logic Low = VIL, H = Logic High = VIH, VHH = 8.5 - 9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Note: WP#/ACC must be high when writing to upper two and lower two sectors (PL256N: 0, 1,132, and 133; PL127/129N:
0, 1, 68, and 69)
9.1.1 Dual Chip Enable Device Description and Operation (PL129N Only)
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate processors with a limited addressable range. This product operates as two separate devices in a single package and requires the processor to address half of the memory space with one chip enable and the remaining memory space with a second chip enable. For more details on the addressing features of the Dual CE# device refer to Table 8.3 on page 16 for the PL129N Sector and Memory Address Map. Dual chip enable products must be setup appropriately for each operation. To place the device into the active state either CE1# or CE2# must be set to VIL. To place the device in standby mode, both CE1# and CE2# must be set to VIH. Table 9.2 describes the required state of each control pin for any particular operation.
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Preliminary
Table 9.2
Operation Read
Dual Chip Enable Device Operation
RESET# H WP#/ACC X X (Note 2) X X X X Addresses (A21 - A0)
AIN
CE1# CE2# OE# WE# L H L H H L X X H L H L H L X X L H
DQ15 - DQ0
DOUT
Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
H X H X X
L X H X X
H H H L VID
AIN
DIN
X X X
AIN
High-Z High-Z High-Z
DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH,VID = 11.5-12.5 V, VHH = 8.5 - 9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. 2.
The sector and sector unprotect functions may also be implemented by programming equipment. WP#/ACC must be high when writing to the upper two and lower two sectors.
9.2
Asynchronous Read
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered.
9.2.1 Non-Page Random Read
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming the addresses have been stable for at least tACC - tOE time).
9.2.2 Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted (= VIH), the reassertion of CE# for subsequent access has access time of tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping Amax - A3 constant and changing A2 - A0 to select the specific word within that page. Address bits Amax - A3 select an 8-word page, and address bits A2 - A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. See Table 9.3 for details on selecting specific words.
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Preliminary
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Reads from the memory array may be performed in conjunction with the Erase Suspend and Program Suspend features. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any nonerase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. After the device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank.
Table 9.3
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Word Selection within a Page
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
9.3
Autoselect
The Autoselect mode allows the host system to access manufacturer and device identification, and verify sector protection, through identifier codes output from the internal register (separate from the memory array) on DQ15-DQ0. This mode is primarily intended to allow equipment to automatically match a device to be programmed with its corresponding programming algorithm. When verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 9.5). The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment can then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register. Note that if a Bank Address (BA) on the four uppermost address bits is asserted during the third write cycle of the Autoselect command, the host system can read Autoselect data from that bank and then immediately read array data from the other bank, without exiting the Autoselect mode. To access the Autoselect codes, the host system must issue the Autoselect command. The Autoselect command sequence can be written to an address within a bank that is either in the read or erase-suspend-read mode. The Autoselect command cannot be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations or page modes. The system must write the reset command to return to the read mode (or erase-suspendread mode if the bank was previously in Erase Suspend).
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Preliminary
See Table 15.1 for command sequence details.
Table 9.4
Description Manufacturer ID Read Cycle 1 Device ID: Read Cycle 2 Read Cycle 3
Autoselect Codes
DQ15 to DQ0
CE# A - A5 - OE# WE# max A10 A9 A8 A7 A6 A3 A2 A1 A0 See Note A12 A4 L L L H BA X X X L L X L L L L L L L 0001h H 227Eh
L
L
H
BA
X
X
X
L
L
L
H
H
H
223Ch (PL256N) L 2220h (PL127N) 2221h (PL129N) 2200h (PL256N) H 2200h (PL127N) 2200h (PL129N) 0000h Unprotected (Neither DYB nor PPB Locked), L 0001h Protected (Either DYB or PPB Locked) - DQ15 - DQ8 = 0 - DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked - DQ6 -Customer Lock Bit 1 = Locked, 0 = Not Locked - DQ5 - Handshake Bit 1 = Reserved, H 0 = Standard Handshake - DQ4 & DQ3 WP# Protection Boot Code 00 = WP# Protects both Top Boot and Bottom Boot Sectors, 11 = No WP# Protection - DQ2 - DQ0 = 0
L
H
H
H
Sector Protection Verification
L
L
H
SA
X
X
X
L
L
L
L
L
H
Indicator Bit
L
L
H
BA
X
X
X
L
L
L
L
L
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: For the PL129N Either CE1# or CE2# must be low to access Autoselect Codes
Software Functions and Sample Code
Table 9.5
Cycle Unlock Cycle 1 Unlock Cycle 2 Autoselect Command Operation Write Write Write
Autoselect Entry
Word Address BAx555h BAx2AAh BAx555h Data 0x00AAh 0x0055h 0x0090h
(LLD Function = lld_AutoselectEntryCmd)
Table 9.6
Cycle Unlock Cycle 1
Notes:
1. 2. 3. Any offset within the device works. BA = Bank Address. The bank address is required. base = base address.
Autoselect Exit
Word Address base + xxxh Data 0x00F0h
(LLD Function = lld_AutoselectExitCmd)
Operation Write
The following is a C source code example of using the autoselect function to read the manufacturer ID. See the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
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Preliminary
/* Here is an example of Autoselect mode (getting manufacturer ID) */ /* Define UINT16 example: typedef unsigned short UINT16; */ UINT16 manuf_id; /* Auto Select Entry */ *((UINT16 *)bank_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */ *((UINT16 *)bank_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */ *((UINT16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */
/* multiple reads can be performed after entry */ manuf_id = *((UINT16 *)bank_addr + 0x000); /* read manuf. id */ /* Autoselect exit */ *((UINT16 *)base_addr + 0x000) = 0x00F0; /* exit autoselect (write reset command) */
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Preliminary
9.4
Program/Erase Operations
These devices are capable of single word or write buffer programming operations which are described in the following sections. The write buffer programming is recommended over single word programming as it has clear benefits from greater programming efficiency. See Table 9.1 on page 17 for the correct device settings required before initiation of a write command sequence. Note the following details regarding the program/erase operations: When the Embedded Program algorithm is complete, the device then returns to the read mode. The system can determine the status of the program operation by using DQ7 or DQ6. See Write Operation Status for information on these status bits. A 0 cannot be programmed back to a 1. Attempting to do so causes the device to set DQ5 = 1 (halting any further operation and requiring a reset command). A succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1. A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend command. Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress. Programming is allowed in any sequence and across sector boundaries for single word programming operation.
9.4.1 Single Word Programming
In single word programming mode, four Flash command write cycles are used to program an individual Flash address. While this method is supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table 15.1 for the required bus cycles and Figure 9.1 for the flowchart. When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See Write Operation Status for information on these status bits. Single word programming is supported for backward compatibility with existing Flash driver software and use of write buffer programming is strongly recommended for general programming. The effective word programming time using write buffer programming is approximately four times faster than the single word programming time.
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Preliminary
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Program Command: Address 555h, Data A0h
Setup Command
Program Data to Address: PA, PD
Program Address (PA), Program Data (PD)
Perform Polling Algorithm
(see Write Operation Status flowchart)
Polling Status = Busy? No Yes Polling Status = Done? No
Yes
Error condition (Exceeded Timing Limits)
PASS. Device is in read mode.
FAIL. Issue reset command to return to read array mode.
Figure 9.1
Single Word Program Operation
Software Functions and Sample Code
Table 9.7
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Note: Base = Base Address.
Single Word Program
Operation Write Write Write Write Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
(LLD Function = lld_ProgramCmd)
The following is a C source code example of using the single word program function. See the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program Command */ *((UINT16 *)base_addr + 0x555) = *((UINT16 *)base_addr + 0x2AA) = *((UINT16 *)base_addr + 0x555) = *((UINT16 *)pa) = /* Poll for program completion */ 0x00AA; 0x0055; 0x00A0; data; /* /* /* /* write write write write unlock cycle 1 unlock cycle 2 program setup command data to be programmed */ */ */ */
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Preliminary
9.4.2 Write Buffer Programming
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard word programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming occurs. At this point, the system writes the number of word locations minus 1 that is loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to Flash confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the write-buffer-page address. All subsequent address/data pairs must fall within the elected-write-buffer-page. The write-buffer-page is selected by using the addresses Amax - A5. The write-buffer-page addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-bufferpage. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer-page, the operation ABORTS.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter decrements for every data load operation. Also, the last data loaded at a location before the Program Buffer to Flash confirm command is programmed into the device. The software takes care of the ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the Sector Address. Any other address/data write combinations abort the Write Buffer Programming operation. The device then goes busy. The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. The write-buffer embedded programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device returns to READ mode. If the write buffer command sequence is entered incorrectly the device enters write buffer abort. When an abort occurs the write-to buffer-abort reset command must be issued to return the device to read mode. The Write Buffer Programming Sequence is ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles.
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Preliminary
Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is approximately four times faster than programming one word at a time. Note that the Secured Silicon, the CFI functions, and the Autoselect Codes are not available for read when a write buffer programming operation is in progress.
Software Functions and Sample Code
Table 9.8
Cycle 1 2 3 4 Description Unlock Unlock Write Buffer Load Command Write Word Count
Write Buffer Program
Word Address Base + 555h Base + 2AAh Program Address Program Address Data 00AAh 0055h 0025h Word Count (N-1)h
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Operation Write Write Write Write
Number of words (N) loaded into the write buffer can be from 1 to 32 words. 5 to 36 Last
Notes:
1. 2. 3. Base = Base Address. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles can be from 6 to 37. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
Load Buffer Word N Write Buffer to Flash
Write Write
Program Address, Word N Sector Address
Word N 0029h
The following is a C source code example of using the write buffer program function. See the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Write Buffer Programming Command */ /* NOTES: Write buffer programming limited to 16 words. */ /* All addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. A flash page begins at addresses */ /* evenly divisible by 0x20. */ UINT16 *src = source_of_data; /* address of source data */ UINT16 *dst = destination_of_data; /* flash destination address */ UINT16 wc = words_to_program -1; /* word count (minus 1) */ *((UINT16 *)base_addr + 0x555) = 0x00AA; /* write unlock cycle 1 */ *((UINT16 *)base_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 */ *((UINT16 *)sector_address) = 0x0025; /* write write buffer load command */ *((UINT16 *)sector_address) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *((UINT16 *)sector_address) = 0x0029; /* write confirm command */ /* poll for completion */
/* Example: Write *((UINT16 *)addr *((UINT16 *)addr *((UINT16 *)addr
Buffer Abort Reset */ + 0x555) = 0x00AA; /* write unlock cycle 1 + 0x2AA) = 0x0055; /* write unlock cycle 2 + 0x555) = 0x00F0; /* write buffer abort reset
*/ */ */
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Preliminary
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Issue Write Buffer Load Command: Address 555h, Data 25h
Load Word Count to Program Program Data to Address: SA = wc
wc = number of words - 1
Yes wc = 0?
Confirm command: SA 29h
No Wait 4 s Write Next Word, Decrement wc: PA data , wc = wc - 1 No Write Buffer Abort Desired? Perform Polling Algorithm Yes Write to a Different Sector Address to Cause Write Buffer Abort
(see Write Operation Status flowchart)
Polling Status = Done? No No
Yes
Error?
Yes
Write Buffer Abort? No
Yes
RESET. Issue Write Buffer Abort Reset Command
FAIL. Issue reset command to return to read array mode.
PASS. Device is in read mode.
Figure 9.2 9.4.3 Sector Erase
Write Buffer Programming Operation
The sector erase function erases one or more sectors in the memory array. (See Table 15.1, and Figure 9.3.) The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional sector addresses and sector erase commands can be written. Loading the sector erase buffer can be done in any sequence, and the number of sectors can be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out (tSEA) may or may not
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be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (see DQ3: Sector Erase Timeout State Indicator). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. See Write Operation Status for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 9.3 illustrates the algorithm for the erase operation. See AC Characteristics for the Erase/ Program Operations parameters and timing diagrams.
Software Functions and Sample Code
Table 9.9
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Sector Erase Command
Sector Erase
Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address Data 00AAh 0055h 0080h 00AAh 0055h 0030h
(LLD Function = lld_SectorEraseCmd)
Operation Write Write Write Write Write Write
Unlimited additional sectors can be selected for erase; command(s) must be written within tSEA. The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Sector Erase Command */ *((UINT16 *)base_addr + 0x555) = 0x00AA; *((UINT16 *)base_addr + 0x2AA) = 0x0055; *((UINT16 *)base_addr + 0x555) = 0x0080; *((UINT16 *)base_addr + 0x555) = 0x00AA; *((UINT16 *)base_addr + 0x2AA) = 0x0055; *((UINT16 *)sector_address) = 0x0030; /* /* /* /* /* /* write write write write write write unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ sector erase command */
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Preliminary
Write Unlock Cycles: Write Unlock Cycles: Address 555h, Data AAh Address 555h, Data AAh Address 2AAh, Data 55h Address 2AAh, Data 55h
Unlock Cycle Unlock Cycle 11 Unlock Cycle Unlock Cycle 22
Write Sector Erase Cycles: Write Sector Erase Cycles: Address 555h, Data 80h Address 555h, Data 80h Address 555h, Data AAh Address 555h, Data AAh Address 2AAh, Data 55h Address 2AAh, Data 55h Sector Address, Data 30h Sector Address, Data 30h
Command Cycle Command Cycle 11 Command Cycle Command Cycle 22 Command Cycle Command Cycle 33 Specify first sector for erasure Specify first sector for erasure
No No
Select Select Additional Additional Sectors? Sectors? Yes Yes Write Additional Write Additional Sector Addresses Sector Addresses
* * Each additional cycle must be written within SEA timeout Each additional cycle must be written within t tSEA timeout * * Timeout resets after each additional cycle is written Timeout resets after each additional cycle is written * * The host system may monitor DQ3 or wait SEA to ensure The host system may monitor DQ3 or wait t tSEA to ensure acceptance of erase commands acceptance of erase commands * No limit on number of sectors * No limit on number of sectors * * Commands other than Erase Suspend or selecting Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device additional sectors for erasure during timeout reset device to reading array data to reading array data
No No
Poll DQ3. Poll DQ3. DQ3 = 1? DQ3 = 1? Yes Yes
Yes Yes
Last Sector Last Sector Selected? Selected? No No
Wait s Wait 44 s
Perform Write Operation Perform Write Operation Status Algorithm Status Algorithm
Status may be obtained by reading DQ7, DQ6 and/or DQ2. Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Yes Yes
Done? Done? No No DQ5 = 1? DQ5 = 1? Yes Yes No No Error condition (Exceeded Timing Limits) Error condition (Exceeded Timing Limits)
PASS. Device returns PASS. Device returns to reading array. to reading array.
FAIL. Write reset command FAIL. Write reset command to return to reading array. to return to reading array.
Notes:
1. 2. See Table 15.1 for erase command sequence. See the section on DQ3 for information on the sector erase timeout.
Figure 9.3 9.4.4 Chip Erase Command Sequence
Sector Erase Operation
Chip erase is a six-bus cycle operation as indicated by Table 15.1. These commands invoke the Embedded Erase algorithm, which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definition tables (Table 15.1 and Table 15.2) show the address and data requirements for the chip erase command sequence.
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When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. See Write Operation Status for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
Software Functions and Sample Code
Table 9.10
Cycle 1 2 3 4 5 6 Description Unlock Unlock Setup Command Unlock Unlock Chip Erase Command
Chip Erase
Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0080h 00AAh 0055h 0010h
(LLD Function = lld_ChipEraseCmd)
Operation Write Write Write Write Write Write
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Chip Erase Command */ /* Note: Cannot be suspended */ *((UINT16 *)base_addr + 0x555) = *((UINT16 *)base_addr + 0x2AA) = *((UINT16 *)base_addr + 0x555) = *((UINT16 *)base_addr + 0x555) = *((UINT16 *)base_addr + 0x2AA) = *((UINT16 *)base_addr + 0x000) =
0x00AA; 0x0055; 0x0080; 0x00AA; 0x0055; 0x0010;
/* /* /* /* /* /*
write write write write write write
unlock cycle 1 */ unlock cycle 2 */ setup command */ additional unlock cycle 1 */ additional unlock cycle 2 */ chip erase command */
9.4.5 Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Reading at any address within erasesuspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table 9.18 for information on these status bits.
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Preliminary
After an erase-suspended program operation is complete, the bank returns to the erase-suspendread mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. See Write Buffer Programming and Autoselect for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Software Functions and Sample Code
Table 9.11
Cycle 1 Operation Write
Erase Suspend
Word Address Bank Address Data 00B0h
(LLD Function = lld_EraseSuspendCmd)
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase suspend command */ *((UINT16 *)bank_addr + 0x000) = 0x00B0; /* write suspend command */
Table 9.12
Cycle 1 Operation Write
Erase Resume
Word Address Bank Address Data 0030h
(LLD Function = lld_EraseResumeCmd)
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Erase resume command */ *((UINT16 *)bank_addr + 0x000) = 0x0030; /* write resume command /* The flash needs adequate time in the resume state */ */
9.4.6 Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a Write to Buffer programming operation so that data can read from any nonsuspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the status bits. After the programming operation has been suspended, the system can read array data from any non-suspended sector. The Program Suspend command can also be issued during a programming operation while an erase is suspended. In this case, data can be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area, then user must use the proper command sequences to enter and exit this region.
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The system can also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command (address bits are don't cares) to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming.
Software Functions and Sample Code
Table 9.13
Cycle 1 Operation Write
Program Suspend
Word Address Bank Address Data 00B0h
(LLD Function = lld_ProgramSuspendCmd)
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program suspend command */ *((UINT16 *)base_addr + 0x000) = 0x00B0; /* write suspend command */
Table 9.14
Cycle 1 Operation Write
Program Resume
Word Address Bank Address Data 0030h
(LLD Function = lld_ProgramResumeCmd)
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Program resume command */ *((UINT16 *)base_addr + 0x000) = 0x0030; /* write resume command */
9.4.7 Accelerated Program
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the ACC function. This method is faster than the standard chip program and erase command sequences. The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated chip program and erase should be performed at room temperature (25C 10C). This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a Write-to-Buffer-Abort Reset is required while in Unlock
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Preliminary
Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Sectors must be unlocked prior to raising WP#/ACC to VHH. The WP#/ACC must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device damage can result. Set the ACC pin at VCC when accelerated programming not in use.
9.4.8 Unlock Bypass
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program data, instead of the normal four cycles. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 15.1, Memory Array Commands shows the requirements for the unlock bypass command sequences. During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low Level Driver User's Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
Table 9.15
Cycle 1 2 3 Description Unlock Unlock Entry Command
Unlock Bypass Entry
Operation Write Write Write Word Address Base + 555h Base + 2AAh Base + 555h
*/ */ */
(LLD Function = lld_UnlockBypassEntryCmd)
Data 00AAh 0055h 0020h
/* Example: Unlock Bypass Entry Command */ *((UINT16 *)bank_addr + 0x555) = 0x00AA; /* write unlock cycle 1 *((UINT16 *)bank_addr + 0x2AA) = 0x0055; /* write unlock cycle 2 *((UINT16 *)bank_addr + 0x555) = 0x0020; /* write unlock bypass command /* At this point, programming only takes two write cycles. */ /* Once you enter Unlock Bypass Mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* Unlock Bypass Mode before beginning a different type of */ /* operations. */
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Table 9.16
Cycle 1 2 Description Program Setup Command Program Command
Unlock Bypass Program
Operation Write Write Word Address Base +xxxh Program Address Data 00A0h Program Data
(LLD Function = lld_UnlockBypassProgramCmd)
/* Example: Unlock Bypass Program Command */ /* Do while in Unlock Bypass Entry Mode! */ *((UINT16 *)bank_addr + 0x555) = 0x00A0; /* write program setup command *((UINT16 *)pa) = data; /* write data to be programmed /* Poll until done or error. */ /* If done and more to program, */ /* do above two cycles again. */
*/ */
Table 9.17
Cycle 1 2 Description Reset Cycle 1 Reset Cycle 2
Unlock Bypass Reset
Operation Write Write Word Address Base +xxxh Base +xxxh Data 0090h 0000h
(LLD Function = lld_UnlockBypassResetCmd)
/* Example: Unlock Bypass Exit Command */ *( (UINT16 *)base_addr + 0x000 ) = 0x0090; *( (UINT16 *)base_addr + 0x000 ) = 0x0000;
9.4.9 Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling. The Data# Polling bit, DQ7, indicates to the host system whether an Em-
bedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the writebuffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase Algorithm, Data# polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 can change asynchronously with DQ6 - DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system
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Preliminary
samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6 - DQ0 may be still invalid. Valid data on DQ7 - DQ0 appears on successive read cycles. See the following for more information: Table 9.18, Write Operation Status, shows the outputs for Data# Polling on DQ7. Figure 9.4, Write Operation Status Flowchart, shows the Data# Polling algorithm. Figure 13.13, Data# Polling Timings (During Embedded Algorithms) shows the Data# Polling timing diagram.
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START
Read 1
(Note 6) DQ7=valid data? NO
YES
Erase Operation Complete
Read 1 DQ5=1? NO
YES
Read 2
YES Read3= valid data? NO
YES
Write Buffer Programming?
Read 2
Read 3 Program Operation Failed YES
Programming Operation?
NO Read 3 Device BUSY, Re-Poll
NO (Note 3) (Note 1) DQ6 toggling? YES TIMEOUT (Note 1) DQ6 toggling? NO (Note 2) Device BUSY, Re-Poll Read 2 DQ2 toggling? NO YES DEVICE ERROR (Note 5)
(Note 4) Read3 DQ1=1?
YES
NO
NO
YES
Device BUSY, Re-Poll Erase Operation Complete Device in Erase/Suspend Mode
Read 3
Read3 DQ1=1 AND DQ7 Valid Data?
YES
Write Buffer Operation Failed
NO
Device BUSY, Re-Poll
Notes: 1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6. 2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2. 3. May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation. 4. Write buffer error if DQ1 of last read =1. 5. Invalid state, use RESET command to exit operation. 6. Valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. Data polling algorithm valid for all operations except advanced sector protection.
Figure 9.4
Write Operation Status Flowchart
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Preliminary
DQ6: Toggle Bit I . Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algo-
rithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I can be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP (all sectors protected toggle time), then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7, see DQ7: Data# Polling. If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete. See the following for additional information: Figure 9.4, Write Operation Status Flowchart, Figure 13.14, Toggle Bit Timings (During Embedded Algorithms), Table 9.18, Write Operation Status, and Figure 13.15, DQ2 vs. DQ6. Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
DQ2: Toggle Bit II . The Toggle Bit II on DQ2, when used with DQ6, indicates whether a partic-
ular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 9.18, Write Operation Status to compare outputs for DQ2 and DQ6. See the following for additional information: Figure 9.4, Write Operation Status Flowchart and Figure 13.14, Toggle Bit Timings (During Embedded Algorithms).
Reading Toggle Bits DQ6/DQ2. Whenever the system initially begins reading toggle bit status,
it must read DQ7 - DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erases operation. The system can read array data on DQ7 - DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit might have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through
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successive read cycles, determining the status as described in the previous paragraph. Alternatively, it can choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Figure 9.4, Write Operation Status Flowchart for more details.
DQ5: Exceeded Timing Limits. DQ5 indicates whether the program or erase time has exceeded
a specified internal pulse count limit. Under these conditions DQ5 produces a 1, indicating that the program or erase cycle was not successfully completed. The device may output a 1 on DQ5 if the system tries to program a 1 to a location that was previously programmed to 0. Only an erase operation can change a 0 back to a 1, Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a 1. Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator. After writing a sector erase command sequence,
the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a 0 to a 1. If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See Sector Erase Command Sequence for more details. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is 1, the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 9.18 shows the status of DQ3 relative to the other status bits.
DQ1: Write to Buffer Abort. DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation for more details.
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Preliminary
Table 9.18
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector
Write Operation Status
DQ7 (Note 2) DQ7# 0 INVALID (Not Allowed) Data 1 Data DQ7# 1 Data DQ7# DQ7# DQ7# DQ7# DQ6 Toggle Toggle INVALID (Not Allowed) Data No Toggle Data Toggle No toggle Data Toggle Toggle Toggle Toggle DQ5 (Note 1) 0 0 INVALID (Not Allowed) Data 0 Data 0 0 Data 0 0 1 0 DQ3 N/A 1 INVALID (Not Allowed) Data N/A Data N/A N/A Data N/A N/A N/A N/A DQ2 (Note 2) No toggle Toggle INVALID (Not Allowed) Data Toggle Data N/A Toggle Data N/A N/A N/A N/A DQ1 (Note 4) 0 N/A INVALID (Not Allowed) Data N/A Data N/A N/A Data N/A 0 0 1
Program Suspend Mode (Note 3)
Erase Suspend Mode
Erase-Suspend-Read
Erase Suspended Sector Non-Erase Suspended Sector
Erase-Suspend-Program Erase Suspended Sector Non-Erase Suspended Sector
Erase Suspend Mode
Erase-SuspendRead
Erase-Suspend-Program Write to Buffer (Note 5) BUSY State Exceeded Timing Limits ABORT State
Notes:
1. 2. 3. 4. 5. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. DQ7 a valid address when reading status information. Refer to the appropriate subsection for further details. Data are invalid for addresses in a Program Suspended sector. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
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9.5
Simultaneous Read/Write
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank (except the sector being erased). Figure 13.12, Back-to-back Read/Write Cycle Timings shows how read and write cycles may be initiated for simultaneous operation with zero latency. See the table, DC Characteristics for read-while-program and read-while-erase current specifications.
VCC VSS Mux Amax - A0 Bank A Address
Y-gate
Bank A
X-Decoder
Amax - A0
Bank B Address
Bank B
DQ15-DQ0
DQ15-DQ0
X-Decoder Amax-A0 RESET# WE# CE# WP#/ACC
OE#
State Control and Command Register
RY/BY#
Status DQ15 - DQ0 Control Mux
DQ15-DQ0 DQ15-DQ0 Y-gate
DQ0 - DQ15
Amax-A0
X-Decoder
Bank C Address
Bank C
X-Decoder Amax - A0 Mux Bank D Address Bank D
Note: Amax = A23 (PL256N), A22 (PL127N)
Figure 9.5
Simultaneous Operation Block Diagram for S29PL256N and S29PL127N
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Preliminary
VCC VSS Mux A21 - A0
CE1# = L CE2# = H Bank 1A Bank 1A Address Y-gate X-Decoder
A21 - A0
Bank 1B Address
Bank 1B DQ15 - DQ0
X-Decoder A21 - A0 RESET# WE# CE1# CE2# WP#/ACC
DQ15 - DQ0
OE#
State Control and Command Register
RY/BY#
Status DQ15 - DQ0 Control DQ15 - DQ0 Mux
CE1# = H CE2# = L DQ0 - DQ15 A21 - A0
X-Decoder
X-Decoder A21 - A0 Mux Bank 2B Address Bank 2B
Figure 9.6
Simultaneous Operation Block Diagram for S29PL129N
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DQ15 - DQ0
Bank 2A Address
Bank 2A Y-gate
Preliminary
9.6
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device. Table 8.1 and Table 8.2 indicate the address space that each sector occupies. The device address space is divided into four banks: Banks B and C contain only 128 Kword sectors, while Banks A and D contain both 32 Kword boot sectors in addition to 128 Kword sectors. A bank address is the set of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to uniquely select a sector. ICC2 in DC Characteristics represents the active current specification for the write mode. see AC Characteristics contains timing specification tables and timing diagrams for write operations.
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Preliminary
9.7
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory upon a system reset. See Figure 13.5 and Figure 13.8 for timing diagrams.
9.8
Software Reset
Software reset is part of the command set (see Table 15.1) that also returns the device to array read mode and must be used for the following conditions: 1. 2. 3. 4. 5. To exit Autoselect mode To reset software when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed To exit sector lock/unlock operation. To return to erase-suspend-read mode if the device was previously in Erase Suspend mode. To reset software after any aborted operations
Software Functions and Sample Code
Table 9.19
Cycle Reset Command
Note: Base = Base Address.
Reset
Word Address Base + xxxh Data 00F0h
(LLD Function = lld_ResetCmd)
Operation Write
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User's Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: Reset (software reset of Flash state machine) */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
The following are additional points to consider when using the reset command: This command resets the banks to the read and address bits are ignored. Reset commands are ignored once erasure has begun until the operation is complete. Once programming begins, the device ignores reset commands until the operation is complete The reset command may be written between the cycles in a program command sequence before programming begins (prior to the third cycle). This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command may be also written during an Autoselect command sequence.
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If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ1 goes high during a Write Buffer Programming operation, the system must write the Write to Buffer Abort Reset command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence (see command tables for detail).
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Preliminary
10 Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. This section describes the various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 10.1.
Hardware Methods
Software Methods
Lock Register
(One Time Programmable)
Password Method
(DQ2)
Persistent Method
(DQ1)
(All boot sectors locked)
WP# = VIL
64-bit Password
(One Time Protect)
PPB Lock Bit 0 = PPBs Locked
(Notes 1, 2, 3)
1 = PPBs Unlocked
Memory Array
Sector 0 Sector 1 Sector 2
Persistent Protection Bit (PPD)
(Notes 5, 6)
Dynamic Protection Bit (DYB)
(Notes 7, 8, 9)
PPB 0 PPB 1 PPB 2
DYB 0 DYB 1 DYB 2
Sector N-2 Sector N-1 Sector N
Notes:
1. 2. 3. 4. 5. (Note 4)
PPB N-2 PPB N-1 PPB N
DYB N-2 DYB N-1 DYB N
Bit is volatile, and defaults to 1 on reset. Programming to 0 locks all PPBs to their current state. Once programmed to 0, requires hardware reset to unlock. N = Highest Address Sector. 0 = Sector Protected, 1 = Sector Unprotected.
6. PPBs programmed individually, but cleared collectively. 7. 0 = Sector Protected, 1 = Sector Unprotected. 8. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is 1 (unprotected). 9. Volatile Bits: defaults to user choice upon power-up (see ordering options).
Figure 10.1 44
Advanced Sector Protection/Unprotection S29PL-N_M0_A4 November 23, 2005
S29PL-N MirrorBitTM Flash Family
Preliminary
10.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected, unless otherwise chosen through the DYB ordering option (see Ordering Information). The device programmer or host system must then choose which sector protection method to use. Programming (setting to 0) any one of the following two one-time programmable, non-volatile bits locks the part permanently in that mode: Lock Register Persistent Protection Mode Lock Bit (DQ1) Lock Register Password Protection Mode Lock Bit (DQ2)
Table 10.1
Device DQ15 - 05 DQ4
DYB Lock Boot Bit 0 = sectors power up protected 1 = sectors power up unprotected
Lock Register
DQ3 DQ2 DQ1 DQ0
S29PL256N
Undefined
PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled
Password Protection Mode Lock Bit
Persistent Protection Mode Lock Bit
Secured Silicon Sector Protection Bit
For programming lock register bits see Table 15.2. Notes 1. 2. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank A are disabled, while reads from other banks are allowed until exiting this mode. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed. Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.
3. 4.
After selecting a sector protection method, each sector can operate in any of the following three states: 1. 2. 3. Constantly locked. The selected sectors are protected and cannot be reprogrammed unless PPB lock bit is cleared via a password, hardware reset, or power cycle. Dynamically locked. The selected sectors are protected and can be altered via software commands. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Sections 10.2 - 10.6.
10.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory. Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.
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Preliminary
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. Each PPB is individually programmed and all are erased in parallel. Entry command disables reads and writes for the bank selected. Reads within that bank return the PPB status for that sector. Reads from other banks are allowed while writes are not allowed. All Reads must be performed using the Asynchronous mode. The specific sector addresses (A23 - A14 PL256N and A22 - A14 PL127N/PL129N) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and timesout without programming or erasing the PPB. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank A.
10. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart below.
10.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection scheme for unprotected sectors that have their PPBs cleared (erased to 1). By issuing the DYB Set or Clear command sequences, the DYBs are set (programmed to 0) or cleared (erased to 1), thus placing each sector in the protected or unprotected state respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. Notes 1. The DYBs can be set (programmed to 0) or cleared (erased to 1) as often as needed. When the parts are first shipped, the PPBs are cleared (erased to 1) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering option chosen. If the option to clear the DYBs after power up is chosen, (erased to 1), then the sectorsmay be modified depending upon the PPB state of that sector. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to 0). It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally again. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when WP#/ACC = V HH as they do when WP#/ ACC = VIH.
2. 3. 4. 5.
6.
10.4
Persistent Protection Bit Lock Bit
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to 0), this bit locks all PPB and when cleared (programmed to 1), unlocks each sector. There is only one PPB Lock Bit per device.
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Preliminary
Notes 1. 2. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings.
10.5
Password Protection Method
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a 64-bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB Lock Bit is set 0 to maintain the password mode of operation. Successful execution of the Password Unlock command by entering the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Notes 1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set to prevent access. The Password Program Command is only capable of programming 0s. Programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. The password is all 1s when shipped from the factory. All 64-bit password combinations are valid as a password. There is no means to verify what the password is after it is set. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming. The Password Mode Lock Bit is not erasable. The lower two address bits (A1 - A0) are valid during the Password Read, Password Program, and Password Unlock. The exact password must be entered in order for the unlocking function to occur.
2. 3. 4. 5. 6. 7. 8. 9.
10. The Password Unlock command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to correctly match a password. 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. 12. Password verification is only allowed during the password programming operation. 13. All further commands to the password region are disabled and all operations are ignored. 14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit. 15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank A. Reads and writes for other banks excluding Bank A are allowed. 16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. 17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. 18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device.
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Preliminary
Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h
Unlock Cycle 1 Unlock Cycle 2
Write Enter Lock Register Command: Address 555h, Data 40h
Program Lock Register Data Address XXXh, Data A0h Address 77h*, Data PD
XXXh = Address don't care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock data may only be progammed once.
Wait 4 s
Perform Polling Algorithm
(see Write Operation Status flowchart)
Yes
Done?
No DQ5 = 1? Yes No Error condition (Exceeded Timing Limits)
PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array.
FAIL. Write rest command to return to reading array.
Figure 10.2
Lock Register Program Algorithm
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Preliminary
10.6
Advanced Sector Protection Software Examples
Table 10.2
Unique Device PPB Lock Bit 0 = locked, 1 = unlocked
Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector Any Sector 0 0 0 0 1 1 1 1
Sector Protection Schemes
Sector DYB 0 = protected 1 = unprotected
x x 1 0 x x 0 1
Sector PPB 0 = protected 1 = unprotected
0 0 1 1 0 0 1 1
Sector Protection Status
Protected through PPB Protected through PPB Unprotected Protected through DYB Protected through PPB Protected through PPB Protected through DYB Unprotected
Table 10.2 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In summary, if the PPB Lock Bit is locked (set to 0), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked (reset to 1) through a hardware reset or power cycle. See also Figure 10.1 for an overview of the Advanced Sector Protection feature.
10.7
Hardware Data Protection Methods
The device offers data protection at the sector level via hardware control: When WP#/ACC is at VIL, the four outermost sectors are locked (device specific). There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The following subsections describes these methods:
10.7.1 WP# Method
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP#/ACC pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the outermost boot sectors. The outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device. If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. Note that the WP#/ACC pin must not be left floating or unconnected as inconsistent behavior of the device may result. The WP#/ACC pin must be held stable during a command sequence execution
10.7.2 Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO.
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Preliminary
10.7.3 Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
10.7.4 Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on powerup.
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Preliminary
11
11.1
Power Conservation Modes
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC 0.2 V. The device requires standard access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in DC Characteristics represents the standby current specification
11.2
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC6 in DC Characteristics represents the automatic sleep mode current specification.
11.3
Hardware RESET# Input Operation
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. When RESET# is held at VSS 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS 0.2 V, the standby current is greater. RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
11.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
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Preliminary
12 Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. Note the following general conditions: While the Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank A. On power up, or following a hardware reset, the device reverts to sending commands to the normal address space. Reads outside of sector 0 return memory array data. Sector 0 is remapped from the memory array to the Secured Silicon Sector array. Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit Secured Silicon Sector Mode. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
Table 12.1
Sector Customer Factory
Secured Silicon Sector Addresses
Sector Size 128 words 128 words Address Range 000080h-0000FFh 000000h-00007Fh
12.1
Factory Secured Silicon Sector
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7) permanently set to a 1. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once the product is shipped to the field. These devices are available pre programmed with one of the following: A random, 8-word secure ESN only within the Factory Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service. Both a random, secure ESN and customer code through the Spansion programming service. Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services.
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Preliminary
12.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to 0), allowing customers to utilize that sector in any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional Flash memory space. Please note the following: Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to 1. The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but are available when reading in Banks B through D. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence which return the device to the memory array at sector 0.
12.3
Secured Silicon Sector Entry and Exit Command Sequences
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. See the Command Definition Tables Table 15.1, Memory Array Commands. Table 15.2, Sector Protection Commands for address and data requirements for both command sequences. The Secured Silicon Sector Entry Command allows the following commands to be executed Read customer and factory Secured Silicon areas Program the customer Secured Silicon Sector After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands. Refer to the Spansion Low Level Driver User Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
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Preliminary
Table 12.2
Cycle Unlock Cycle 1 Unlock Cycle 2 Entry Cycle
Note: Base = Base Address.
/* Example: SecSi Sector *((UINT16 *)base_addr + *((UINT16 *)base_addr + *((UINT16 *)base_addr + Entry Command */ 0x555) = 0x00AA; 0x2AA) = 0x0055; 0x555) = 0x0088;
Secured Silicon Sector Entry
Operation Write Write Write Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0088h
(LLD Function = lld_SecSiSectorEntryCmd)
/* write unlock cycle 1 /* write unlock cycle 2 /* write Secsi Sector Entry Cmd
*/ */ */
Table 12.3
Cycle Unlock Cycle 1 Unlock Cycle 2 Program Setup Program
Secured Silicon Sector Program
Word Address Base + 555h Base + 2AAh Base + 555h Word Address Data 00AAh 0055h 00A0h Data Word
(LLD Function = lld_ProgramCmd)
Operation Write Write Write Write
Note: Base = Base Address. /* Once in the SecSi Sector mode, you program */ /* words using the programming algorithm. */
Table 12.4
Cycle Unlock Cycle 1 Unlock Cycle 2 Exit Cycle
Note: Base = Base Address. /* Example: SecSi Sector *((UINT16 *)base_addr + *((UINT16 *)base_addr + *((UINT16 *)base_addr + *((UINT16 *)base_addr +
Exit Command */ 0x555) = 0x00AA; 0x2AA) = 0x0055; 0x555) = 0x0090; 0x000) = 0x0000;
Secured Silicon Sector Exit
Word Address Base + 555h Base + 2AAh Base + 555h Data 00AAh 0055h 0090h
(LLD Function = lld_SecSiSectorExitCmd)
Operation Write Write Write
/* /* /* /*
write write write write
unlock cycle unlock cycle SecSi Sector SecSi Sector
1 2 Exit cycle 3 Exit cycle 4
*/ */ */ */
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
13 Electrical Specifications
13.1 Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground: All Inputs and I/Os except as noted below (Note 1). . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VIO + 0.5 V VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V VIO (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0V ACC (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Notes:
1. 2. 3. 4. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 13.1. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 13.2. Minimum DC input voltage on pin WP#ACC is -0.5 V. During voltage transitions, WP#ACC may overshoot VSS to 2.0 V for periods of up to 20 ns. See Figure 13.1. Maximum DC voltage on pin WP#ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns
Figure 13.1
Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 13.2
Maximum Positive Overshoot Waveform
November 23, 2005 S29PL-N_M0_A4
S29PL-N MirrorBitTM Flash Family
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Preliminary
13.2
Operating Ranges
Wireless (W) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Supply Voltages
VCC Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.7 V to 3.1 V or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to +3.6 V (Note 3)
Notes:
1. 2. 3. Operating ranges define those limits between which the functionality of the device is guaranteed. For all AC and DC specifications, VIO = VCC. Voltage range of 2.7 - 3.1 V valid for PL-N MCP products.
13.3
Test Conditions
Device Under Test CL
Figure 13.3 Table 13.1
Test Setup
Test Specifications
All Speeds 30 VCC = 3.0 V VCC = 3.0 V 5 0.0 - 3.0 VCC/2 VCC/2 Unit pF ns V V V
Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
13.4
Key to Switching Waveforms
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
13.5
Switching Waveforms
All Inputs and Outputs VIO 0.0 V Input VCC/2 Measurement Level VCC/2 Output
Figure 13.4
Input Waveforms and Measurement Levels
13.6
VCC Power Up
Parameter
tVCS tREAD
Description
VCC Setup Time Time between RESET# high and CE# low
Test Setup
Min Min
Speed
250 200
Unit
s ns
Notes:
1. 2. VCC ramp rate must exceed 1 V/400 s. VIO is internally connected to VCC.
VCC
VCC min
tVCS
VIH
RESET#
tRead
CE#
Figure 13.5
VCC Power-Up Diagram
November 23, 2005 S29PL-N_M0_A4
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Preliminary
13.7
DC Characteristics
13.7.1 DC Characteristics (VCC = 2.7 V to 3.6 V)
(CMOS Compatible)
Parameter Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VHH VOL VOH VLKO Parameter Description (Notes) Input Load Current Output Leakage Current VCC Active Read Current (1, 3) VCC Active Write Current (3) VCC Standby Current VCC Reset Current Automatic Sleep Mode (4) VCC Active Read-While-Write Current (1) Test Conditions VIN = VSS to VCC, VCC = VCC
max
Min (Note 2) (6)
Typ (Note 2)
Max 2.0 1.0
Unit A A mA mA A A A mA mA mA V V V V V
VOUT = VSS to VCC, OE# = VIH VCC = VCC max (6) OE# = VIH, VCC = VCC max (1, 6) OE# = VIH, WE# = VIL CE# (7), RESET#, WP#/ACC = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V OE# = VIH 5 MHz 5 MHz 30 25 20 300 20 35 27 40 MHz -0.5 2.0 8.5 6
45 50 40 500 40 50 55 10 0.8 VCC + 0.3 9.5 0.1
VCC Active Program-While-EraseOE# = VIH Suspended Current (5) VCC Active Page Read Current Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (5) OE# = VIH, 8 word Page Read VCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V VCC = 3.0 V 10% (6) IOL = 100 A, VCC = VCC min (6) IOH = -100 A (6) VCC - 0.2 2.3
2.5
V
Notes:
1. 2. 3. 4. 5. 6. 7. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical VCC=3.0 V, TA = +25C. ICC is active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC +30 ns. Typical sleep mode current is 1 A. Not 100% tested. The data in the table is for VCC range 2.7 V to 3.6 V (recommended for standalone applications). CE1# and CE2# for the PL129N.
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
13.7.2 DC Characteristics (VCC = 2.7 V to 3.1 V)
(CMOS Compatible)
Parameter Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 VIL VIH VHH VOL VOH VLKO Parameter Description (Notes) Input Load Current Output Leakage Current VCC Active Read Current (1, 2) VCC Active Write Current (2, 3) VCC Standby Current (2) VCC Reset Current (2) Automatic Sleep Mode (2, 4) VCC Active Read-While-Write Current (1, 2) VCC Active Program-While-EraseSuspended Current (2, 5) VCC Active Page Read Current (2) Input Low Voltage Input High Voltage Test Conditions VIN = VSS to VCC, VCC = VCC
max
Min (6)
Typ
Max 2 1
Unit A A mA mA A A A mA mA mA V V V V V
VOUT = VSS to VCC, OE# = VIH VCC = VCC max (6) OE# = VIH, VCC = VCC max (1, 6) OE# = VIH, WE# = VIL CE# (7), RESET#, WP#/ACC = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.1 V OE# = VIH OE# = VIH OE# = VIH, 8 word Page Read VCC = 2.7 to 3.6 V VCC = 2.7 to 3.6 V IOL = 100 A, VCC = VCC min (6) IOH = -100 A (6) VCC - 0.2 2.3 40 MHz -0.5 2.0 8.5 5 MHz 5 MHz 28 22 20 300 20 33 24 6
40 40 40 500 40 45 45 9 0.8 VCC + 0.3 9.5 0.1
Voltage for ACC Program Acceleration VCC = 3.0 V 10% (6) Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (5)
2.5
V
Notes:
1. 2. 3. 4. 5. 6. 7. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. Maximum ICC specifications are tested with VCC = VCC max, TA = TAmax. Typical ICC specifications are with typical VCC=2.9 V, TA = +25C. ICC active while Embedded Erase or Embedded Program is in progress. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 1 A. Not 100% tested. Data in table is for VCC range 2.7 V to 3.1 V (recommended for MCP applications) CE1# and CE2# for the PL129N.
November 23, 2005 S29PL-N_M0_A4
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Preliminary
13.8
AC Characteristics
13.8.1 Read Operations
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC Read Cycle Time (1) CE#, OE# = VIL OE# = VIL Description (Notes) Test Setup Min Max Max Max Max Max Max Min Min Min Speed Options 65 65 65 65 25 25 70 70 70 70 30 30 16 16 5 0 10 80 80 80 80 30 30 Unit ns ns ns ns ns ns ns ns ns ns
tACC Address to Output Delay tCE Chip Enable to Output Delay (5)
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (3) Output Enable to Output High Z (1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (3) Read Toggle and Data# Polling
tOEH Output Enable Hold Time (1)
Notes:
1. 2. 3. 4. 5. Not 100% tested. See Figure 13.3 and Table 13.1 for test specifications Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. For 70pf Output Load Capacitance, 2 ns is added to the above tACC ,tCE ,tPACC ,tOE values for all speed grades CE1# and CE2# for the PL129N.
13.8.2 Read Operation Timing Diagrams
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 13.6
Read Operation Timings
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
A22 to A3
Same page Addresses
A2 to A0
Aa
Aa+1
Aa+2
Aa+3
Aa+4
Aa+5
Aa+6
Aa+7
tACC
tCE
CE# OE#
tOEH
tOE tDF
WE#
High-Z
tPACC tOH
tPACC tOH
Da+1
tPACC tOH
Da+2
tPACC tOH
Da+3
tPACC tOH
Da+4
tPACC tOH
Da+5
tPACC tOH
Da+6
tOH
Da+7
Output
Da
Figure 13.7 13.8.3 Hardware Reset (RESET#)
Parameter
Page Read Operation Timings
All Speed Options Description Unit
JEDEC
Std.
tRP tRH
RESET# Pulse Width Reset High Time Before Read (See Note)
Min Min
30 200
s ns
Note: Not 100% tested.
CE#, OE# tRH RESET# tRP
Figure 13.8
Reset Timings
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Preliminary
13.8.4 Erase/Program Timing
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVHH tRB tBUSY tWEP tSEA tESL tPSL tASP tPSP Write Cycle Time (1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation Accelerated Programming Operation Sector Erase Operation VHH Rise and Fall Times Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Noise Pulse Margin on WE# Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Toggle Time During Sector Protection Toggle Time During Programming Within a Protected Sector Description (Notes) Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max Max Max Max Max Typ Typ Speed Options 65 65 70 70 0 15 35 0 30 0 10 0 0 0 40 25 0 40 24 1.6 250 0 90 3 50 20 20 100 1 80 80 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec ns ns ns ns s s s s s
Notes:
1. 2. 3. 4. Not 100% tested. In program operation timing, addresses are latched on the falling edge of WE#. See Program/Erase Operations for more information. Does not include the preprogramming time.
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# tWPH
Read Status Data (last two cycles)
PA
PA
tCH
tWHWH1
A0h
Status
DOUT tRB
VCC tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address
Figure 13.9
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 13.10
Accelerated Program Timing Diagram
November 23, 2005 S29PL-N_M0_A4
S29PL-N MirrorBitTM Flash Family
63
Preliminary
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase Status DOUT
tBUSY RY/BY# tVCS VCC
tRB
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status)
Figure 13.11
Chip/Sector Erase Operation Timings
tWC Addresses tAS CE#
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tAS tCPH
tAH
tCP
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles
Figure 13.12 Back-to-back Read/Write Cycle Timings
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 13.13
Data# Polling Timings (During Embedded Algorithms)
tAHT Addresses
tAS
tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 13.14
Toggle Bit Timings (During Embedded Algorithms)
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Preliminary
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 13.15
DQ2 vs. DQ6
13.8.5 Erase and Programming Performance
Parameter (Notes) 128 Kword Sector Erase Time 32 Kword Device Condition VCC ACC VCC ACC VCC Chip Erase Time ACC VCC ACC VCC ACC VCC ACC VCC Chip Programming Time using 32-Word Buffer (3) ACC Erase Suspend/Erase Resume Program Suspend/Program Resume Typ (Note 1) 1.6 1.6 0.3 0.3 202 (PL256N) 100 (PL127N) 100(PL129N) 130 (PL256N) 65 (PL127N) 65 (PL129N) 40 24 9.4 6 300 192 157.3 (PL256N) 78.6 (PL127N) 78.6 (PL129N) 100 (PL256N) 50 (PL127N) 50 (PL129N) Max (Note 2) 7 7 4 4 900 (PL256N) 450 (PL127N) 450 (PL129N) 512 (PL256N) 256 (PL127N) 256 (PL129N) 400 240 94 60 3000 1920 315 (PL256N) 158 (PL127N) 158 (PL129N) 200 (PL256N) 100 (PL127N) 100 (PL129N) <20 <20 s Unit Comments (Notes)
Excludes 00h programming prior to erasure (4)
s
Word Programming Time
s
Excludes system level overhead (5)
Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time
s
s
s
Excludes system level overhead (5)
s s
Notes:
1. 2. 3. 4. 5. 6. 7. 8. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 10,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. Under worst case conditions of 90C, VCC = 2.7 V, 100,000 cycles. All values are subject to change. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 15.1 and Table 15.2 for further information on command definitions. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions. See Application Note Erase Suspend/Resume Timing for more details. Word programming specification is based upon a single word programming operation not utilizing the write buffer.
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
13.8.6 BGA Ball Capacitance
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 7 8 8 Max 10 12 11 Unit pF pF pF
Notes:
1. 2. Sampled, not 100% tested. Test conditions TA = 25C, f = 1.0 MHz.
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Preliminary
14 Commonly Used Terms
Term ACC Definition ACCelerate. A special purpose input signal which allows for faster programming or erase operation when raised to a specified voltage above VCC. In some devices ACC may protect all sectors when at a low voltage. Most significant bit of the address input [A23 for 256 Mbit, A22 for 128 Mbit, A21 for 64 Mbit] Least significant bit of the address input signals (A0 for all devices in this document). Operation where signal relationships are based only on propagation delays and are unrelated to synchronous control (clock) signal. Read mode for obtaining manufacturer and device information as well as sector protection status. Section of the memory array consisting of multiple consecutive sectors. A read operation in one bank, can be independent of a program or erase operation in a different bank for devices that offer simultaneous read and write feature. Smaller size sectors located at the top and or bottom of Flash device address space. The smaller sector size allows for finer granularity control of erase and protection for code or parameters used to initiate system operation after power on or reset. Location at the beginning or end of series of memory locations. See synchronous read. 8 bits Common Flash Interface. A Flash memory industry standard specification [JEDEC 137A and JESD68.01] designed to allow a system to interrogate the Flash to determine its size, type and other performance parameters. Zero (Logic Low Level) Special purpose register which must be programmed to enable synchronous read mode Synchronous method of burst read whereby the device reads continuously until it is stopped by the host, or it has reached the highest address of the memory array, after which the read address wraps around to the lowest memory array address Returns bits of a Flash memory array to their default state of a logical One (High Level). Halts an erase operation to allow reading or programming in any sector that is not selected for erasure Ball Grid Array package. Spansion LLC offers two variations: Fortified Ball Grid Array and Fine-pitch Ball Grid Array. See the specific package drawing or connection diagram for further details. Synchronous (burst) read operation in which 8, 16, or 32 words of sequential data with or without wraparound before requiring a new initial address. Multi-Chip Product. A method of combining integrated circuits in a single package by stacking multiple die of the same or different devices. The programmable area of the product available for data storage. SpansionTM trademarked technology for storing multiple bits of data in the same transistor. Group of words that may be accessed more rapidly as a group than if the words were accessed individually.
Amax Amin Asynchronous Autoselect
Bank
Boot sector Boundary Burst Read Byte CFI Clear Configuration Register
Continuous Read Erase Erase Suspend/Erase Resume
BGA
Linear Read MCP Memory Array MirrorBitTM Technology Page
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S29PL-N MirrorBitTM Flash Family
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Preliminary
Term
Definition Asynchronous read operation of several words in which the first word of the group takes a longer initial access time and subsequent words in the group take less page access time to be read. Different words in the group are accessed by changing only the least significant address lines. Sector protection method which uses a programmable password, in addition to the Persistent Protection method, for protection of sectors in the Flash memory device. Sector protection method that uses commands and only the standard core voltage supply to control protection of sectors in the Flash memory device. This method replaces a prior technique of requiring a 12V supply to control the protection method. Stores data into a Flash memory by selectively clearing bits of the memory array to leave a data pattern of ones and zeros. Halts a programming operation to read data from any location that is not selected for programming or erase. Host bus cycle that causes the Flash to output data onto the data bus. Dynamic storage bits for holding device control information or tracking the status of an operation. An area consisting of 256 bytes in which any word may be programmed once, and the entire area may be protected once from any future programming. Information in this area may be programmed at the factory or by the user. Once programmed and protected there is no way to change the secured information. This area is often used to store a software readable identification such as a serial number. Use of one or more control bits per sector to indicate whether each sector may be programmed or erased. If the Protection bit for a sector is set the embedded algorithms for program or erase ignore the program or erase commands related to that sector. An Area of the memory array in which all bits must be erased together by an erase operation. Mode of operation in which a host system may issue a program or erase command to one bank, that embedded algorithm operation may then proceed while the host immediately follows the embedded algorithm command with reading from another bank. Reading may continue concurrently in any bank other than the one executing the embedded algorithm operation. Operation that progresses only when a timing signal, known as a clock, transitions between logic levels (that is, at a clock edge). Separate power supply or voltage reference signal that allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs. Mode that facilitates faster program times by reducing the number of command bus cycles required to issue a write operation command. In this mode the initial two Unlock write cycles, of the usual 4 cycle Program command, are not required - reducing all Program commands to two bus cycles while in this mode. Two contiguous bytes (16 bits) located at an even byte boundary. A double word is two contiguous words located on a two word boundary. A quad word is four contiguous words located on a four word boundary.
Page Read
Password Protection
Persistent Protection
Program Program Suspend/Program Resume Read Registers
Secured Silicon
Sector Protection
Sector
Simultaneous Operation
Synchronous Operation
VersatileIOTM (VIO)
Unlock Bypass
Word
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Preliminary
Term
Definition Special burst read mode where the read address wraps or returns back to the lowest address boundary in the selected range of words, after reading the last Byte or Word in the range, e.g. for a 4 word range of 0 to 3, a read beginning at word 2 would read words in the sequence 2, 3, 0, 1. Interchangeable term for a program/erase operation where the content of a register and or memory location is being altered. The term write is often associated with writing command cycles to enter or exit a particular mode of operation. Multi-word area in which multiple words may be programmed as a single operation. A Write Buffer may be 16 to 32 words long and is located on a 16 or 32 word boundary respectively. Method of writing multiple words, up to the maximum size of the Write Buffer, in one operation. Using Write Buffer Programming results in greater than eight times faster programming time than by using single word at a time programming commands. Allows the host system to determine the status of a program or erase operation by reading several special purpose register bits.
Wraparound
Write
Write Buffer
Write Buffer Programming
Write Operation Status
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S29PL-N_M0_A4 November 23, 2005
Preliminary
15 Appendix
This section contains information relating to software control or interfacing with the Flash device. For additional information and assistance regarding software, see Additional Resources, or explore the Web at www.amd.com and www.fujitsu.com.
Table 15.1
Command Sequence (Notes) Read (7) Reset (8) Manufacturer ID Autoselect (9) Device ID (10) Indicator Bits Cycles
Memory Array Commands
Fifth Addr Data Sixth Addr Data
1 1 4 6 4
Bus Cycles (Notes 1 - 6) First Second Third Fourth Addr Data Addr Data Addr Data Addr Data RA RD XXX F0 555 AA 2AA 55 [BA]555 90 [BA]X00 0001 555 555 AA AA AA AA 29 AA AA AA B0 30 98 AA A0 80 80 98 90 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 [BA]555 [BA]555 555 SA 555 555 555 90 90 A0 25 F0 80 80
[BA]X01 227E [BA]X0E [BA]X03 PA SA (Note 11) Data WC
(Note [BA]X0F 2200 10)
Program Write to Buffer (17) Program Buffer to Flash Write to Buffer Abort Reset (17) Chip Erase Sector Erase Program/Erase Suspend (14) Program/Erase Resume (15) CFI Query (16) Unlock Bypass Entry Unlock Bypass Program (12, 13) Unlock Unlock Bypass Sector Erase (12, 13) Bypass Unlock Bypass Erase (12, 13) Mode Unlock Bypass CFI (12, 13) Unlock Bypass Reset Secured Silicon Sector Command Definitions Secured Silicon Sector Entry (18) Secured Secured Silicon Sector Program Silicon Secured Silicon Sector Read Sector Secured Silicon Sector Exit (19)
4 555 6 555 1 SA 3 555 6 555 6 555 1 BA 1 BA 1 [BA]555 3 555 2 XX 2 XX 2 XX 1 BA 2 XX 3 2 1 4 555 XX RA 555
PA
PD
WBL
PD
555 555
AA AA
2AA 2AA
55 55
555 SA
10 30
2AA PA SA XXX XXX
55 PD 30 10 00
555
20
AA 2AA 55 A0 PA data data AA 2AA 55
555
88
555
90
XX
00
Legend: X = Don't care. RA = Read Address. RD = Read Data. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse whichever happens later. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Notes: 1. See (Table 9.1) for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the password verify command, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15 - DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 - PWD0. 5. Unless otherwise noted, these address bits are don't cares: PL127: A22 - A15; 129N: A21 - A15; PL256N: A23 - A14. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock.
SA = Sector Address. PL127/129N = A22 - A15; PL256N = A23 - A15. BA = Bank Address. PL256N = A23 - A21; PL127N = A22 - A20; PL127N = A21 - A20. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1.
9.
10. 11. 12. 13. 14.
15. 16.
The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See Autoselect. Device IDs: PL256N = 223Ch; PL127N = 2220h; PL129N = 2221h. See Autoselect. The Unlock Bypass command sequence is required prior to this command sequence. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37.
November 23, 2005 S29PL-N_M0_A4
S29PL-N MirrorBitTM Flash Family
71
Preliminary
17. Command sequence resets device for next command after writeto-buffer operation. 18. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 19. The Exit command must be issued to reset the device into read mode. Otherwise the device hangs. 20. The following mode cannot be performed at the same time. Autoselect/CFI/Unlock Bypass/Secured Silicon. Command sequence resets device for next command after write-to-buffer operation.
21. Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for PL256N. 22. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state.
Table 15.2
Command Sequence (Notes) Lock Register Command Set Definitions Lock Register Command Set Entry (25) Lock Register Bits Program (26) Lock Register Lock Register Bits Read Lock Register Command Set Exit (27) Password Protection Command Set Definitions Password Protection Command Set Entry (25) Password Program Password Cycles
Sector Protection Commands
Second Addr Data 2AA 00 XX 2AA 55 data 00 55 555 60 Bus Cycles (Notes 1 - 6) Third Fourth Fifth Sixth Seventh Addr Data Addr Data Addr Data Addr Data Addr Data 555 40
First Addr Data 555 XX 00 XX 555 XX AA A0 data 90 AA
3 2 1 2 3 2
Password Read 4 00 Password Unlock 7 00 Password Protection 2 XX 90 XX Command Set Exit (27) Non-Volatile Sector Protection Command Set Definitions Non-Volatile Sector Protection 3 555 AA 2AA Command Set Entry (25) PPB Program 2 XX A0 [BA]SA All PPB Erase (22) 2 XX 80 00 PPB PPB Status Read 1 [BA]SA RD(0) Non-Volatile Sector Protection 2 XX 90 XX Command Set Exit (27) Global Non-Volatile Sector Protection Freeze Command Set Definitions Global Volatile Sector Protection Freeze 3 555 AA 2AA Command Set Entry (25) 2 XX A0 XX PPB Lock PPB Lock Bit Set Bit PPB Lock Bit Status Read 1 BA RD(0) Global Volatile Sector Protection Freeze 2 XX 90 XX Command Set Exit (27) Volatile Sector Protection Command Set Definitions Volatile Sector Protection 3 555 AA 2AA Command Set Entry (25) DYB Set 2 XX A0 [BA]SA DYB Clear 2 XX A0 [BA]SA DYB DYB Status Read 1 [BA]SA RD(0) Volatile Sector Protection 2 XX 90 XX Command Set Exit (27) Legend: X = Don't care RA = Read Address. RD = Read Data. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse whichever happens later. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address. PL127/129N = A22 - A15; PL256N = A23 - A15
PWD0/ 00/01 PWD1/ A0 02/03 PWD2/ PWD3 PWD0 01 PWD1 25 00 03 00
02 00
PWD2 PWD0
03 01
PWD3 PWD1
02
PWD2
03
PWD3
00
29
55 00 30 00
[BA]555
C0
55 00 00
555
50
55 00 01 00
[BA]555
E0
BA = Bank Address. PL256N = A23 - A21; PL127N = A22 - A20; PL127N = A21 - A20. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. PWD3 - PWD0 = Password Data. PD3 - PD0 present four 16 bit combinations that represent the 64-bit Password RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1.
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S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
Notes: 1. See (Table 9.1) for description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15 - DQ8 are don't care in command sequences, except for RD, PD, WD, PWD, and PWD3 - PWD0. 5. Unless otherwise noted, these address bits are don't cares: PL127: A22 - A15; 129N: A21 - A15; PL256N: A23 - A14. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See Autoselect. 10. The data is 0000h for an unlocked sector and 0001h for a locked sector. 11. Device IDs: PL256N = 223Ch; PL127N = 2220h; PL129N = 2221h. 12. See Autoselect. 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address.
15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 17. The entire four bus-cycle sequence must be entered for which portion of the password. 18. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode.The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 19. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 20. Command is valid when device is ready to read array data or when device is in autoselect mode.The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 21. The entire four bus-cycle sequence must be entered for which portion of the password. 22. The ALL PPB ERASE command pre-programs all PPBs before erasure to prevent over-erasure of PPBs. 23. WP#/ACC must be at VHH during the entire operation of this command. 24. Command sequence resets device for next command after writeto-buffer operation. 25. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26. If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode. 27. The Exit command must be issued to reset the device into read mode. Otherwise the device hangs.
15.1
Common Flash Memory Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft-ware algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and back-ward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address (BA)555h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 12.3 - 12.6) within that bank. All reads outside of the CFI address range, within the bank, return non-valid data. Reads from other banks are allowed, writes are not. To terminate reading CFI data, the system must write the reset command. The following is a C source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available at www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development guidelines.
/* Example: CFI Entry command */ *((UINT16 *)bank_addr + 0x555) = 0x0098; /* Example: CFI Exit command */ *((UINT16 *)bank_addr + 0x000) = 0x00F0; /* write CFI entry command */
/* write cfi exit command
*/
November 23, 2005 S29PL-N_M0_A4
S29PL-N MirrorBitTM Flash Family
73
Preliminary
For further information, please see the CFI Specification (see JEDEC publications JEP137-A and JESD68.01and CFI Publication 100). Please contact your sales office for copies of these documents.
Table 15.3
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
CFI Query Identification String
Description
Query Unique ASCII string QRY Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
Table 15.4
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0006h 0009h 000Bh 0000h 0003h 0003h 0002h 0000h
System Interface String
Description
VCC Min. (write/erase) D7 - D4: volt, D3 - D0: 100 millivolt VCC Max. (write/erase) D7 - D4: volt, D3 - D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 15.5
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h Data 0019h (PL256N) 0018h (PL127N) 0018h (PL129N) 0001h 0000h 0006h 0000h 0003h 0003h 0000h 0000h 0001h 007Dh (PL256N) 003Dh (PL127N) 003Dh (PL129N) 0000h 0000h 0004h 0003h 0000h 0000h 0001h
Device Geometry Definition
Description
Device Size = 2N byte Flash Device Interface description (see CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (see the CFI specification or CFI publication 100)
Erase Block Region 2 Information (see the CFI specification or CFI publication 100)
Erase Block Region 3 Information (see the CFI specification or CFI publication 100)
74
S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
Table 15.6
Addresses 40h 41h 42h 43h 44h 45h 46h 47h 48h Data 0050h 0052h 0049h 0031h 0034h 0010h 0002h 0001h 0000h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string PRI Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1 - 0) 0 = Required, 1 = Not Required Silicon Technology (Bits 5 - 2) 0100 = 0.11 m Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400 mode, 04 = 29LV800 mode 07 = New Sector Protect mode, 08 = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors except Bank A Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7 - D4: Volt, D3 - D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7 - D4: Volt, D3 - D0: 100 mV Top/Bottom Boot Sector Flag 00h = No Boot, 01h = Dual Boot Device, 02h = Bottom Boot Device, 03h = Top Boot Device Program Suspend 0 = Not supported, 1 = Supported Unlock Bypass 00 = Not Supported, 01=Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read mode Maximum 2N ns Hardware Reset Low Time-out not during an embedded algorithm to read mode Maximum 2N ns Erase Suspend Time-out Maximum 2N s Program Suspend Time-out Maximum 2N s Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank A Region Information. X = Number of sectors in bank
49h
0008h (PL-N) 0073h (PL256N) 003Bh (PL127N) 003Bh (PL129N) 0000h 0002h (PL-N) 0085h 0095h 0001h 0001h 0001h 0007h 000Fh 000Eh 0005h 0005h 0004h 0013h (PL256N) 000Bh (PL127N) 000Bh (PL129N) 0030h (PL256N) 0018h (PL127N) 0018h (PL129N) 0030h (PL256N) 0018h (PL127N) 0018h (PL129N) 0013h (PL256N) 000Bh (PL127N) 000Bh (PL129N)
4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h
58h
59h
Bank 1 Region Information. X = Number of sectors in bank
5Ah
Bank 2 Region Information. X = Number of sectors in bank
5Bh
Bank 3 Region Information. X = Number of sectors in bank
November 23, 2005 S29PL-N_M0_A4
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75
Preliminary
16 Revisions
Revision A0 (February 28, 2005)
Initial Release
Revision A1 (August 8, 2005)
Performance Characteristics
Updated Package Options
MCP Look-Ahead Connection Diagram
Corrected Pinout
Memory Map
Added Sector and Memory Address Map for S29PL127N
Device Operation Table
Added Dual Chip Enable Device Operation Table
VCC Power Up
Updated tVCS. Added VCC ramp rate restriction
DC Characteristics
Updated typical and maximum values.4
Revision A2 (October 25, 2005)
Global
Changed data sheet status from Advance Information to Preliminary. Removed Byte Address Information
Distinctive and Performance Characteristics
Removed Enhanced VersatileI/O, updated read access times, and Package options.
Logic Symbol and Block Diagram
Removed VIO from Logic Symbol and Block Diagram.
Erase and Programming Performance
Updated table.
Write Buffer Programming
Updated Write Buffer Abort Description.
Operating Ranges
Updated VIO supply voltages.
DC characteristics
Updated ICC1, ICC4, ICC6.
76
S29PL-N MirrorBitTM Flash Family
S29PL-N_M0_A4 November 23, 2005
Preliminary
Revision A3 (November 14, 2005)
Ordering Information
Updated table
Valid Combinations Table
Updated table
Revision A4 (November 23, 2005)
Logic Symbols
Removed VIO from the illustrations
Block Diagram
Removed VIO from the illustration
PL129N Sector and Memory Address Map
Updated Address Ranges for Banks 2A and 2B
November 23, 2005 S29PL-N_M0_A4
S29PL-N MirrorBitTM Flash Family
77
pSRAM Type 2
16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) 128Mbit (8M Word x 16-bit)
PRELIMINARY
Features
Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM
Product Information
Density 16Mb 16Mb 32Mb 32Mb 64Mb 64Mb 128Mb VCC Range 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V Standby (ISB1, Max.) 80 A 80 A 100 A 100 A TBD 120 A TBD Operating (ICC2, Max.) 30 mA 35 mA 35 mA 40 mA TBD 45 A TBD Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS and Page Mode
Publication Number pSRAM_15
Revision A
Amendment 2
Issue Date February 3, 2005
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
Preliminary
17 Pin Description
Pin Name CS1#, CS2 OE# WE# LB#, UB# A0 - A19 (16M) A0 - A20 (32M) A0 - A21 (64M) A0 - A22 (128M) I/O0-I/O15 VCC/VCCQ VSS/VSSQ NC DNU Description Chip Select Output Enable Write Enable Lower/Upper Byte Enable Address Inputs Data Inputs/ Outputs Power Supply Ground Not Connection Do Not Use I/O I I I I
I
I/O -- -- -- --
18 Power Up Sequence
1. 2. Apply power. Maintain stable power (VCC min.=2.7V) for a minimum 200 s with CS1#=high or CS2=low.
19 Timing Diagrams
19.1 Power Up
VCC Min.200 s
CS1#
CS2
Power Up Mode
~~ ~~
~ ~
~ ~
VCC(Mi ) n
Normal Operation
Note: After VCC reaches VCC(Min.), wait 200 s with CS1# high. Then the device gets into the normal operation.
Figure 19.1
n VCC(Mi )
Power Up 1 (CS1# Controlled)
Min. 200s
VCC
CS1#
Power Up Mode
~ ~
CS2
~~ ~~
~ ~
Normal Operation
Note: After VCC reaches VCC(Min.), wait 200 s with CS2 low. Then the device gets into the normal operation.
Figure 19.2.
Power Up 2 (CS2 Controlled)
February 3, 2005 pSRAM_15_A2
pSRAM Type 2
79
Preliminary
20 Functional Description
Mode Deselected Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Standby Active Active Active Active Active Active Active Active
Legend: X = Don't care (must be low or high state).
21 Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature Symbol VIN , VOUT VCC PD TA Ratings -0.2 to VCC +0.3 V -0.2 to 3.6 V 1.0 -40 to 85 Unit V V W C
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than one second may affect reliability.
22 DC Recommended Operating Conditions
Symbol VCC VSS VIH VIL Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage Min 2.7 0 2.2 (16Mb, 32Mb, 128Mb) 0.8 x VCC (64Mb -0.2 (Note 3) Typ 2.9 0 -- -- Max 3.1 0 VCC + 0.3 (16Mb, 32Mb, 128Mb) VCC + 0.2 (64Mb) (Note 2) 0.6 V Unit
Notes:
1. 2. 3. 4. TA=-40 to 85C, unless otherwise specified. Overshoot: VCC+1.0V in case of pulse width 20ns. Undershoot: -1.0V in case of pulse width 20ns. Overshoot and undershoot are sampled, not 100% tested.
23 Capacitance
Ta = 25C, f = 1 MHz
Symbol CIN CIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min -- -- Max 8 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
80
pSRAM Type 2
pSRAM_15_A2 February 3, 2005
Preliminary
24 DC and Operating Characteristics
24.1 Common
Item Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Symbol ILI ILO VOL VOH Test Conditions VIN=VSS to VCC CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC IOL=2.1mA IOH=-1.0mA Min -1 -1 -- 2.4 Typ -- -- -- -- Max 1 1 0.4 -- Unit A A V V
24.2 16M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Min Typ Max Unit -- -- 7 mA
Cycle time=Min, IIO=0mA, 100% duty, Async CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Page Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
--
--
30
mA
35
mA
Standby Current (CMOS)
ISB1 (See Note)
--
--
80
A
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
24.3 32M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Min Typ Max Unit -- -- 7 mA
Cycle time=Min, IIO=0mA, 100% duty, Async CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Page Cycle time=tRC+3tPC, IIO=0 mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
--
--
35
mA
40
mA
Standby Current (CMOS)
ISB1 (See Note)
--
--
100
A
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
24.4 64M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Min Typ Max Unit -- -- TBD mA
Cycle time=Min, IIO=0mA, 100% duty, Async CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Page Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
--
--
TBD
mA
45
mA
Standby Current (CMOS)
ISB1 (See Note)
--
--
120
A
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
February 3, 2005 pSRAM_15_A2
pSRAM Type 2
81
Preliminary
24.5 128M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled) Min Typ -- -- Max TBD Unit mA
--
--
TBD
mA
--
--
TBD
A
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms from the time when standby mode is set up.
25 AC Operating Conditions
25.1 Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 V to 2.2 V (16Mb, 32Mb, 128Mb); 0.3 V to 2.2 V (64Mb) Input rising and falling time: 5ns (16Mb, 32Mb); 3ns (64Mb, 128Mb) Input and output reference voltage: 1.5V (16Mb, 32Mb); 0.5 x VCC (64Mb, 128Mb) Output load (See Figure 25.1): 50pF (16Mb, 32Mb); 30pF (64Mb, 128Mb)
Dout
CL
Note: Including scope and jig capacitance.
Figure 25.1
Output Load
82
pSRAM Type 2
pSRAM_15_A2 February 3, 2005
Preliminary
26 AC Characteristics
(Ta = -40C to 85C, VCC = 2.7 to 3.1 V)
Speed Bins Symbol tRC tAA tCO tOE tBA tLZ Read tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW Write tBW tWP tWR tWHZ tDW tDH tOW Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Time Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Parameter Min 70 -- -- -- -- 10 10 5 0 0 0 5 (3 for 64Mb) 25 -- 70 60 0 60 60 55 (Note 1) 0 0 30 0 5 70ns Max -- 70 70 35 70 -- -- -- 25 25 25 -- -- 20 -- -- -- -- -- -- -- 25 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: tWP (min)=70ns for continuous write operation over 50 times.
27 Timing Diagrams
27.1 Read Timings
tRC
Address
tOH tAA
Data Out
Previous Data Valid
Data Valid
Note: Address Controlled, CS1#=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL.
Figure 27.1
Timing Waveform of Read Cycle(1)
February 3, 2005 pSRAM_15_A2
pSRAM Type 2
83
Preliminary
tRC
Address
tAA tOH tCO
CS1#
CS2
tHZ
UB#, LB#
tBA tBHZ
OE#
tOLZ tBLZ tLZ
tOE tOHZ
Data out
Note: WE#=VIH.
High-Z
Data Valid
Figure 27.2.
Address1)
Timing Waveform of Read Cycle(2)
Valid Address
A1~A0
Valid Address
Valid Address
Valid Address
Valid Address
tAA
tPC
CS1#
CS2
tCO
OE#
High Z tOE tPA
Data Valid Data Valid Dat a Valid Dat a Valid
tOHZ
DQ15~DQ0
Note: 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21, 128Mb: A2 ~ A22. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. tOE(max) is met only when OE# becomes enabled after tAA(max). If invalid address signals shorter than min. tRC are continuously repeated for over 4s, the device needs a normal read timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4s.
Figure 27.3.
Timing Waveform of Page Cycle (Page Mode Only)
84
pSRAM Type 2
pSRAM_15_A2 February 3, 2005
Preliminary
27.2 Write Timings
tWC Address tCW tWR
CS1#
CS2
tAW tBW tWP WE# tAS Data in High-Z tWHZ tDW Data Valid tOW tDH HighZ
UB#, LB#
Data out
Data Undefined
Figure 27.4.
Write Cycle #1 (WE# Controlled)
tWC
Address
tAS tCW tAW tWR
CS1#
CS2
tBW tWP
UB#, LB#
WE#
tDW tDH
Data in Data out
Data Valid
High-Z
Figure 27.5.
Write Cycle #2 (CS1# Controlled)
February 3, 2005 pSRAM_15_A2
pSRAM Type 2
85
Preliminary
tWC
Address
tAS tCW tAW tWR
CS1#
CS2
tBW tWP(1) WE# tDW Data in Data Valid tDH
UB#, LB#
Data out
High-Z
Figure 27.6.
Timing Waveform of Write Cycle(3) (CS2 Controlled)
tWC
Address
tCW tWR
CS1#
tAW
CS2
UB#, LB#
tAS tBW tWP
WE#
tDW tDH
Data in Data out
Notes:
1.
Data Valid
High-Z
2. 3. 4.
A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. tCW is measured from the CS1# going low to the end of write. tAS is measured from the address valid to the beginning of write. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1# or WE# going high.
Figure 27.7.
Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
86
pSRAM Type 2
pSRAM_15_A2 February 3, 2005
Preliminary
28 pSRAM Revision Summary
28.1 Revision A0 (February 16, 2004)
Initial release
28.2 Revision A1 (June 11, 2004)
DC and Operation Characteristics Updated tables for all densities.
28.3 Revision A2 (February 3, 2005)
Product Information Updated table DC Recommended Operating Conditions Updated VIH min and max specifications AC Operation Conditions Updated test conditions specifications
February 3, 2005 pSRAM_15_A2
pSRAM Type 2
87
Preliminary
29 MCP Revision Summary
Revision A0 (August 24, 2005)
Initial Release
Revision A1 (November 11, 2005)
Updated the MCP wrapper to reflect MCP template and format Updated the package drawing and all references to it to FEB084 Changed the sector sizes in the Performance Characteristic table.
Revision A2 (December 6, 2005)
Updated the Flash module.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abovementioned uses of the products. Any semiconductor device has an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion LLC product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c)2005 Spansion LLC. All rights reserved. Spansion, the Spansion logo, and MirrorBit are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
88
S71PL512ND0 MirrorBitTM Flash Family
S71PL512ND0_00_A2 December 6, 2005

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